1. Field of the Invention
The present invention relates to a disk drive such as a hard-disk drive (HDD) and a control method thereof, and more particularly to a disk drive with a cache memory and a control method thereof.
2. Description of Related Art
A hard-disk drive (HDD) is typically used as an auxiliary storage unit for an information processor (hereinafter referred to as a host). An HDD may include a cache memory for temporarily storing data supplied from the host or temporarily storing data read out from a magnetic disk until it is transferred to the host, and a controller for performing cache control.
If write data is supplied from the host, the controller retains the write data supplied in the cache memory and then releases the host from the write process. Concurrently, the controller controls further processing of the write data so that the write data retained in the cache memory is sequentially written to a magnetic disk (hereinafter referred to as a medium). Furthermore, the controller performs the reading of data from the medium in which it expects that the host will request and retains the read data in the cache memory. If data to be read is retained in the cache memory when there is a read request from the host, the data will be supplied to the host. If such cache control is performed, the access speed of an HDD is improved.
Conventional low-end HDDs often adopt a method in which the intervention of the microprocessor (hereinafter referred to as a local MPU) of the HDD is minimized with respect to the peripheral interfacing processes while the host interface controller (HIC) performs the majority of the peripheral interfacing processes by hardware. This conventional approach often improves the performance of the HDD by reducing the command overhead time.
For example, the data transfer between an external host and a cache memory may be performed under the control of an HIC without intervention of a local MPU while the data transfer between the medium and the cache memory may be performed by a hard disk controller (HDC) under the control of the local MPU.
More specifically, when data is written to a medium by a write command from a host, the following steps may be performed:
(1) Once the HIC transfers data from the host to the cache memory, the HIC notifies the local MPU that a command from the host was received. In response to this, the local MPU commands the HDC to write the data stored in the cache memory onto the medium. Thus, the HDC transfers the data stored in the cache memory to the medium.
(2) The HIC then notifies the local MPU that the data transfer from the host to the cache memory has been completed, while the HDC notifies the local MPU that the write operation to the medium has been completed.
The operations of the HIC and the local MPU are described in further detail below. If the HIC receives a write command from the host, it will start the data transfer to the cache memory immediately without intervention from the local MPU and notify the local MPU that the transfer of data from the host to the cache memory has started. When the data transfer is completed and also the cache memory has an acceptable vacancy (e.g., 1 block) for the next write command, the HIC notifies the local MPU that the command is completed. This notification is performed so that when the next write command is received, it can be transferred immediately to the cache memory, which is the standard for systems having an integrated device electronics (IDE) interface.
In the aforementioned operation, if there is a sufficient vacancy on the cache memory, the HIC by itself will notify the host of the completion of the command to the host, regardless of the write process being performed by the local MPU. The HIC receives the next write command from the host and performs data transfer based on the next write command. This allows the HIC to fetch as many commands as possible from the host, thereby improving the performance of the HDD. In order to perform the aforementioned operation, a command queue is provided in the cache memory for retaining the command type in the cache memory.
FIG. 2 shows the structure of the command queue in the cache memory. According to FIG. 2, Q (=1, 2, . . . , and n) denotes a queue address and A, B, C, D, . . . , and N denote commands retained in the cache memory. In the command queue, older commands are cached in order of A, B, C, D, . . . , and N. Each time a command is received, the number of queue addresses is increased, and if older commands are executed in sequence, the number of queue addresses will be decreased. The management of the command queue is performed by the HIC, and the local MPU fetches the commands with the queue addresses.
If the local MPU commands the HDC to write data to a medium, the write command retained in the command queue is executed by the HDC, and data is written to the medium. Also, the data read out from the medium is transferred to the cache memory by the HDC and is transferred to the host by the HIC.
Unfortunately, an HDD using this conventional method which retains the write commands in a command queue has several drawbacks.
For example, since the write commands retained in the command queue are executed in sequence to write data to the medium, the same write operation to the medium is repeated in the case where the same command is repeatedly issued and retained in the command queue, and consequently, unnecessary access is implemented. Referring now to the command queue structure shown in FIG. 2, in the case where the same command is repeatedly cached in the cache memory (e.g., command A, command B, command A, command B, command A, command B, . . . ), the data written to the medium by older commands A and B is completely overwritten by execution of newer commands A and B, and consequently, only the data written to the medium by the last commands A and B will remain. This leads to unnecessary access resulting in performance degradation.
In such a write operation performed by an HDD, the time required for data transfer, such as latency time, is incommensurably long compared with the data transfer between a cache memory and a host.